A dedicated memory mapped IO region is set aside at the top of the address space (albeit it could quite easily be in any location) ie. The ZPU Evo creates up to two distinct regions within the address space depending on configuration, to provide a system bus and a wishbone bus.Īll models have the system bus instantiated which starts at cpu address 0 and expands up-to the limit imposed by the configurable maximum address bit (ie. Existing ZPU designs either provide a system bus or a wishbone bus whereas the Evo provides both. The ZPU has a linear address space with all memory and IO devices directly addressable within this space. The following sections indicate some of the features and changes to original ZPU designs. The original CPU's all handled their memory requirements in-situ or part of the state machine whereas the Evo submits a request to the MXP whenever a memory operation is required. The design differs though due to caching and implementation of a Memory Transaction Processor where all Memory/IO operations (except for direct Instruction reads if dual-port instruction bus is enabled) are routed.
2byte to 1 byte evom code#
The ZPU Evo follows on from the ZPU Medium and Flex and areas of the code are similar, for example the instruction decoding. There is room for a lot more improvements such as stack cache, SDRAM to L2 burst mode, parallel instruction execution (ie. implementation of a LoaD Increment Repeat instruction). upto 5 IM instructions executed in 1 cycle) or for extended multi-byte instructions (ie. Instruction expansion can be seen by the inclusion of a close coupled L1 cache where multiple instruction bytes are sourced and made available to the CPU which in turn can be used for optimization (ie. Connectivity can be seen via implementation of both System and Wishbone buses, allowing for connection of many opensource IP devices. Comparisons can be made with the original ZPU designs in the gallery below paying attention to the CoreMark score which seems to be the defacto standard now. This came about as I needed a CPU for an emulator of a vintage computer i am writing which would act as the IO processor to provide Menu, Peripheral and SD services.Īn example of the performance of the ZPU Evo can be seen using CoreMark which returns a value of 22.2 100MHz on Altera fabric using BRAM and for Dhrystone 13.2DMIPS. This document describes another design which I like to deem as the ZPU Evo(lution) model whose focus is on performance, connectivity and instruction expansion. Additional designs were produced by external developers such as the Flex and ZPUino variations, each offering enhancements to the original design such as Wishbone interface, performance etc. Zylin produced two designs which it made open source, namely the Small and Medium ZPU versions. It is a microprocessor intended for FPGA embedded applications with minimal logic element and BRAM usage with the sacrifice of speed of execution. The ZPU is a 32bit Stack based microprocessor and was originally designed by Øyvind Harboe from ( ) and original documentation can be found on the ( \(microprocessor\)).
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